Solutions Assessment
Microcontrollers Assessment |
Development Solutions Assessment |
Why a core assessment?
Assessing the value of a microcontroller core in a fair and objective way is a tricky project. In fact, an objective appreciation of the performances of such a core requires to evaluate several criteria that may be interdependent, and to take into account the conditions under which the evaluation is complete.
The intrinsic performance of a microcontroller core mostly results from the combination of, on one hand, the efficiency of its instruction set architecture and its associated C-Compiler, and on the other hand, the performance of the selected libraries - standard-cell and RAM/ROMs.
It is crucial to select properly a benchmark and then to appreciate the performance at the right “level”. The selection of an appropriate benchmark as representative as possible for the application-level requirements is important to get relevant results for each microcontroller.
 Fore more details, download the article "Selecting an embedded MCU: How to avoid evaluation trap?"
Global Process
Frequency assessment (A)
Basically, any processor can succeed to execute even a very complex task if it runs at a sufficiently high frequency. However, this frequency could be unachievable in the targeted technology or could result in a so high power consumption that does not match power specification of the circuit.
So, the real goal is not to evaluate the maximum frequency but the capability to reach the performance required by the application i.e. the capability to execute the program in a given amount of time. This performance is the factor of the processor frequency and the processing power of the core. So, the way to evaluate the speed is to define the performance to reach, to get the processing power of the core and to deduce the required frequency.
Processing power
The processing power can be assessed by running an appropriate benchmark (e.g. Dhrystone)
How can you get the information?
- Figures from Rock’n Roll Brochures: Rock’n Roll Family, Flip80251 Typhoon etc.
- Integrated Development Environment (IDE): µVision3 or RIDE from Keil or Raisonance website
Example for Dolphin’s microcontrollers
| Reference conditions |
Benchmark: Dhrystone V2.1
Number of loops: 200 |
| Flip8051 Cyclone |
0.074 DMIPS/MHz |
| Flip80251 Typhoon |
0.296 DMIPS/MHz |
| APS32 |
0.71 DMIPS/MHz |
Frequency (B)
The maximum frequency can be found by synthesizing the core. It depends on technology process, standard cells library, synthesis conditions, and the core architecture.
How can you get the information?
- The figure depends on a lot of conditions. It is preferable to perform its own synthesis with the library used for the project to evaluate the maximum frequency of the core.
Power consumption assessment (C)
Many factors will greatly affect the power specifications listed on the processor core’s datasheet, including the target technology, the cell library used to generate the core, and the execution activity imposed on the processor during power simulation. Moreover, it is more relevant to compare the power efficiency of a core (µA/DMIPS) instead of comparing the power consumption (µW/MHz) which is not representative of what a processor does in a single cycle. Once again, it is important to compare the power consumption of “CPU + memories” instead of CPU alone.
How can you get the information?
- Figures from Rock’n Roll Brochures: Rock’n Roll Family, Flip80251 Typhoon etc.
- Power analysis performed by Dolphin in the targeted technology in a given set of conditions
Example
for Dolphin’s
MCU
| Reference conditions |
Benchmark: Dhrystone V2.1/Typical conditions: TSMC 0.18µm process, 1.8V, 25°C
Standard cells library: SESAME uHD
Post synthesis, including wire load and clock tree (+30% of consumption) |
| Flip8051 Cyclone |
44 µA/MHZ, 595 µA/DMIPS |
| Flip80251 Typhoon |
62 µA/MHz, 209 µA/DMIPS |
| APS32 |
34 µA/MHz, 48 µA/DMIPS (including automatic clock gating) |
Area assessment
The real question is not to evaluate only the core area but the silicon area of the core and its embedded memories (program and data). So, area assessment is absolutely linked with the evaluation of the code density.
Code density (D)
Code density of a core should be evaluated with a relevant benchmark (program) i.e. with a benchmark representative of the final application.
How can you get the information?
- Figures from Rock’n Roll Brochures: Rock’n Roll Family, Flip80251 Typhoon etc.
- IDE (µVision3 or RIDE) from Keil or Raisonance website
Example for Dolphin’s microcontrollers
| Reference conditions |
Benchmark: Dhrystone V2.1 |
| Flip8051 |
Cyclone 9,820 bytes |
| Flip80251 Typhoon |
5,136 bytes |
Core area (E)
The core area depends on the technological process, the standard cells library and the timing constraints (target frequency)
How can you get the information?
- Figures from Rock’n Roll Brochures: Rock’n Roll Family, Flip80251 Typhoon etc.
- Synthesis performed by Dolphin in the targeted technology in a given set of conditions
Example for Dolphin’s microcontrollers
| Reference conditions |
Slow case conditions: TSMC 0.18 µm process, 1.62 V, 125°C
Standard cells library: SESAME uHD, post synthesis
Configuration: processor (cf technical note from Dolphin) |
| Flip8051 Cyclone |
0.079 mm2 |
| Flip80251 Typhoon |
0.148 mm2 |
| APS32 |
0.112 mm2 |
Development Solutions assessment
Efficiency of development tools
The goal is to evaluate the ability of the debug solution to find bugs quickly (tracing, breakpoints etc…)
How can you get the information?
Evaluation of the IDE thanks to the tools available on Dolphin’s partners’ website.
Quality of debug solutions
The goal is to have the features needed in the debug solution, and to evaluate the reliability/maturity of these solutions. The ease of use of the solution is necessary to enable a quick evaluation.
How can you get the information?
- PRIDE Brochure
- Presentation Sheet of the solutions
- Product Primer of the solutions
- Discover & Buy Kit
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