Libraries Differentiators

RAM

REGISTER FILES

ROM

STANDARD CELL LIBRARIES

PROVEN EXPERTISE

When Dolphin Integration delivered it’s first memory instance more than twenty five years ago, it was one of the first IP providers.
Today, Dolphin is one of the top 5 independent library providers.
Our engineering team currently includes about 150 engineers.
Our libraries benefit from proprietary techniques, often patented, for ensuring the best performance trade-offs.
The architecture of our libraries have proven their robustness in multiple foundries, IDMs, to major players and specialized foundries.

ENSURING SOC SILICON SUCCESS ON FIRST PASS

Our libraries benefit from our proprietary qualification process VFP ™ (Virtual Fab Process), which ensures that simulations are predictive of the robustness and of the yield. VFP ™ is the efficient substitute to the inadequate Trial-and-Error qualification process on silicon.
We guarantees that libraries perform in accordance with Specifications, through our unique “Trust Commitment” clause.
We provides Engineering Support to help SoC Integrators build an efficient memory subsystem.
Our engineers have developed a unique validation method to anticipate yield drop due to the mismatch.
Our engineers have developed a calculation method of the OCV to be applied on its cell libraries.

COMPLETENESS OF OFFERING

FlexLib is the comparable architecture for methodical constructions of voltage and energy islets including:

Reduced Cell Stem Library
SpRAM and DpRAM
Metal programmable ROM
SpRfile, DpRFile
Regulators, integrated switches… for structuring an efficient power management network (upstream and downstream regulators)
Detectors: BIST, BISD, ECC for structuring an efficient test network

A SET OF INNOVATIONS AND PATENTED SOLUTIONS

Low power architectures specifically designed to enable robust low voltage operation, with characterizations taking into account physical phenomena linked to low voltage
Design optimization for minimizing leakage of RAMs, standard cells… (LLA)
Bit-cell mastery for reducing power consumption of memory planes (divided by 4) while improving speed and reducing area (XAM)
New approach for optimizing Performance, Power and Area of any logic block through the fusion of library stems with optimal adaptation at "logic path level”
Patented SESAME BIV (Battery Interface Voltage) designed with 3.3 V transistors for direct battery supply
Patented D Flip Flop: less sensitive to clock edges and guarantying the functionality at very low voltage
Patented High density Flip Flop: the spinner cell system
Patented Multi-bit ROM bit-cell (tROMet)
Patented Dual-bit ROM bit-cell (1/2T sROMet)

FIND THE OPTIMAL PERFORMANCE TRADE-OFFS!

Dolphin Integration has continuously enriched their offering of embedded Memories and Standard Cell Libraries so as to offer Off-the-Shelf products from 180 nm down to 40 nm endowed with differentiated optimizations to address a diversity of SoC requirements

Typical gains High Density - Low Power Panoply	Core VDD +/-10%	Power Consumption (uA) at Nominal Voltage *	Area Reduction *
180 nm G	1.8 V	Divided by up to 2	Up to 20%
130 nm G	1.2 V	Save up to 40%	Up to 30%
65 nm LP	1.2 V	Divided by up to 2	Up to 10%

Typical gains Low Power - Dual Voltage Panoply	Core VDD +/-10%	Power Consumption (uA) at Nominal Voltage *	Power Consumption (uA) at Low voltage *
180 nm G	1.8 V 1.1 V	Divided by up to 3.5	Divided by up to 7
130 nm G	1.2 V 0.9 V	Save up to 30%	Divided by up to 2

Typical gains Ultra Low Leakage Panoply	Core VDD +/-10%	Leakage *
180 nm G	1.8 V	Divided by up to 1,000
130 nm G	1.2 V	Divided by up to 1,000

* Comparison with free libraries

Standard cells Memories