Flash announcement
Availability of StorageWare™ for facilitating the selection and integration of small memories
Grenoble, France - April 8, 2011
StorageWare™ is a library of synthesizable models (RTL in Verilog-HDL) for storage systems, which combines state-of-the-art performance and productivity improvements in logic design.
Today’s SOCs tend to need hundreds of small memory banks implementing functionalities such as register files, FIFOs, LIFOs requiring various logic wrappers, glue logic and solutions such as BIST, ECC…
The integration of such scattered memory instances into logic islets and complete SoCs raises challenges involving the architect, then the designers and the SoC Integrators as well as test engineers.
This trend highlights the need for standard cell library users to be provided with a new solution for structuring their logic by optimizing registers and small memories: StorageWare™.
Storageware™ is a constructive aid for engineers’ productivity:
The easiest integration in your SoC
- Synthesizable models grant larger and wider flexibility than hard macros, allowing greater flexibility to the SoC architect in addressing special needs
- Designers can start using synthesizable models and later decide to switch for hard macros called from the 1PRFile AURA & DPRFile ERIS generators
- StorageWare includes a platform of digital wrappers to easily implement banking of instances while selecting the optimized configuration in terms of Area, Speed and Power consumption
- Guidelines for insertion of synthesizable models whatever the fabrication process and EDA framework
Completeness of functionalities
- The StorageWare platform provides expanders of memory functionalities: FIFO & LIFO wrapper, ECC wrapper, HD-BIST wrapper…
Fast prototyping
- Synthesizable models from StorageWare can be used for FPGA prototyping
Have a glimpse at the Presentation Sheet. | 
Printer-friendly version
