Flash announcement
Launch of a 65 nm compiler for Dual Port Register Files reaching the highest density
Grenoble, France and Netanya, Israel - September 12, 2011
The ERIS architecture for Dual Port Register File compiler, already available in 130 nm, is now adapted to the 65 nm and its shrunk version at 55 nm. Specifically suited for mainstream applications ranging from embedded microcontrollers to high-density consumer and portable devices, the ERIS generator is cost-optimized. It meanwhile provides the smallest power consumption, leaving far behind the competing generators currently available.
As an example, one instance of 416 bits achieves a power consumption as low as 2.83 uW for a density of 0.0052 mm2 in 65 nm.
Such performances are due to its unique architecture optimizing the periphery area for outstanding area gain.
About the benefits of DpRFile ERIS compiler in 65 nm LP
Reduced die cost
- Up to 25% denser than traditional memory register!
- Routing allowed upwards from Metal 3
The smallest power consumption
- Up to 40% less power (for both dynamic and leakage consumption) than traditional memory register
- Low Voltage operation down to 0.81 V for additional savings
The easiest integration in your SoC
- All the flexibility of 2 independent read and 2 independent write ports (2R/2W)
- Library of synthesizable models through StorageWare ™ for facilitating the selection and integration of synthesizable and generatable storage blocks
- Speed up to 600 Mhz in worst case
For more information, feel free to download DpRFile ERIS presentation sheet or to contact Elsa BERNARD-MOULIN: ragtime@dolphin-ip.com
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