Flash announcement
Proven on silicon: A Panoply of Memories and Standard Cells to divide dynamic power by 5 at 180 nm
Grenoble, France - November 25, 2011
With the release of its latest 180 nm Panoply of standard cells and memories, Dolphin Integration paves the way for a new generation of ultra low power SoCs in mature processes.
This panoply already celebrated at various foundries in diverse 180 nm flavors reaches TSMC, Silterra, Dongbu and now the EEPROM process at SMIC: it satisfies the stringent cost and power minimization for the MCU and wireless devices, as well as the needs of mobile phones and smart cards.
Dolphin Integration’s Panoply is based on a comprehensive set of silicon-proven products:
- Single Port RAM generator
- Standard Cell Library and associated Islet Construction Kit
- Metal programmable ROM generator
- Efficient Power Regulators
As the result of Dolphin’s 26 years’ low power expertise, this Panoply enables a power reduction by a factor of 5 compared with the other libraries available.
Highlights on the capabilities offered for SoC power sensitive architectures:
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Low voltage operation
- Down to 1.0 V
- Dual Voltage variant of the Panoply also available
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Safe integration and right-on-first pass silicon
- Proven on silicon
- Patented standard cell architecture
- Proprietary methodology to validate the sRAM bit-cell SPICE model behavior at low voltage
- SpRAM architecture specifically designed to limit dynamic IR Drop
- Models of peak current delivered for free
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Power islets
- Low Power cells for power gating and state retention of logic blocks
- Embedded power switches for partial or complete shut down of memory blocks
- UPF/CPF compatibility
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Reduced die cost
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Standard Cell library compatible with 1P3M SoC implementation
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For memories, deliverables are compatible with Top Metals 4 or 5 or +
Have a quick look at the Presentation Sheets of these products :
For requiring an access to the online memory generators, please click here |