Flash announcement
Leakage divided by more than 250 at 180 nm eLL with our Panoply of memory and standard cells
Grenoble, France - August 26, 2011
As electronic intelligence is pervading battery-powered consumer and industrial devices, their Systems On Chip must come up with more complex features - while limiting the impact on power consumption and die cost.
Such power sensitive applications must rely on architectures of Silicon IPs which enable:
- The best combination of logic density and power consumption
- Islets with diverse low power modes: multi voltage, retention, extinction
- Capability for efficient operation at ultra low voltage
Dolphin Integration is the unique provider to address all of such challenges at the architectural level with the launch of a complete Panoply of Memories and Standard Cells for the new 180 nm eLL process at TSMC.
Dolphin Integration's Panoply is a comprehensive set of silicon IPs for low power and Dual Voltage
- Single Port RAM generator
- Standard Cell library of the celebrated Reduced Cell Stem flavor
- Metal programmable ROM generator
- Efficient Power Regulators
Benchmark results of Dolphin SpRAM versus Standard SpRAM at 180 nm
- 5% denser
- Twice less leaky in G process, 250 times less leaky in eLL process!
- 3 times less dynamic power in G and eLL process!
- Support for low voltage down to 1.2 V for additional power savings
For building ultra low power islets at 180 nm eLL
- Low voltage operation enabled down to 1.2 V
- Low Power cells for power gating and state retention of logic blocks
- Embedded power switches for partial or complete shut down of memory blocks
- UPF/CPF compatibility
For right-on-first-pass silicon
- TSMC 9000 qualification
- Design methodology ensuring functionality at low voltage
Ask for more information on product performances and key features, please click here
| 
Printer-friendly version
