Communication
Contacts
Offering
Investors
Careers
Libraries of Standard cells and Memories
Logic virtual components
Analog virtual components
Test structures
Hardware/Software Codesign
Virtual test & diagnostic
Hardware/Software Codesign
Layout verification
My MEDAL
Quadrant of skills
SoC Integration
Custom Fabless Supplier
 
 

Search dolphin:

silicium estimator
Libraries Vision > Flash announcement

Flash announcement

A density record for Dual Port Register Files saving up to 30% of area

 

Grenoble, France - April 1, 2011

The innovative ERIS architecture for Dual Port Register Files is the attractive alternative to conventional Dual Port memory generators at 130 nm.

The DpRFolder™ ERIS (2R/2W) allows power and cost reductions, while satisfying the speed constraint of many high-speed applications from high-density consumers and portable devices.

Highlights

  • Reduced die cost
    • Up to 30% denser than older solutions on the market
    • Optional High Density BIST for industrial test of instances
    • Layout compatibility between various foundries
  • The easiest integration in your SoC
    • All the flexibility of 2 independent read and 2 independent write ports (2R/2W)
    • Library of synthesizable models through StorageWare™ for facilitating the selection and integration of small memories
  • The Dolphin quality
    • Guaranteed design yield for the memories in your circuits

Have a quick look at the Presentation Sheet.

To request an access to the DpRFile ERIS generator, please click here.