Catalogue > Ultra Low Leakage Panoply 180 / 160 / 152 nm
Panoply 180 / 160 / 152 nm: Ultra Low Leakage
Reducing the static power consumption is a permanent concern for SoC Integrators, in both nomad and battery-driven consumer and industrial applications. This leakage challenge can only be addressed at the architectural level with a complete solution for all elements of the logic design. To facilitate the implementation of leakage optimized SoC architectures, Dolphin Integration offers the Ultra Low Leakage (ULL) Panoply.
Available for the 180 and 130 nm processes, the ULL Panoply includes memories, standard cells libraries and regulators. These Silicon IPs minimize leakage power of Systems on Chip, extends battery life together with ensuring low cost manufacturing.
⇒ See possible Architectural implementation
| Typical gains |
Core VDD
+/-10% |
Leakage * |
| 180 nm G |
1.8 V |
Divided by up to 1,000 |
* Comparison with traditional libraries
Catalogue
Due to the diversity of foundries, process nodes and variants addressed, make sure to check with us the availability of any Panoply.
⇒ See our complete Catalogue for 180 nm
Architectural implementation
Choosing the appropriate regulators optimized for the best efficiency together with leakage optimized Silicon IPs ensures the longest battery operation and the lowest leakage. Dolphin Integration proposes a chip level solution for leakage management in the form of a Panoply of Silicon IPs together with an innovative approach for leakage optimized power management including upstream regulators, the Interface des Prairies (IdP) and downstream regulators. The following schematics propose a low leakage architectural implementation:
- The static power consumption is reduced by embedding low static power consumption memories and libraries of standard cells
- Creation of islets with up to 3 operating modes depending on the sequence of activity: Active, Retention, Extinction.
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