Catalogue > LP-DV Panoply 65 nm

Panoply 65 nm: Low Power - Dual Voltage

To satisfy demanding customers, Fabless companies are facing the need to embed always more features in their chip. The increasing complexity of SoC results in both an increased silicon area and an increased power consumption. To be efficient, power management must be managed at the architectural level.
To facilitate power optimized implementation, Dolphin Integration is introducing a Panoply of Memories, Registers, Standard Cells and regulators which uniquely offer Dual Voltage capability and are delivered with characterizations for 1.2 V and 0.9 V in the 65 nm LP process node.

⇒ See possible Architectural implementation

Typical gains	Core VDD +/-10%	Consumption at Nominal Voltage *	Consumption at Low Voltage *
65 nm LP	1.2 V 0.9 V	Save up to 30%	Divided by up to 2

* Comparison with traditional libraries

Catalogue

Due to the diversity of foundries, process nodes and variants addressed, make sure to check with us the availability of any Panoply.

Product Type	Product Name	Capacity	Foundry	Presentation sheet	Evaluation kit

Single Port Memory Register	1PRFile AURA-SB-HD/RR DV	128 - 40 k	TSMC LP …	Available	Available

⇒ See our complete Catalogue for 65 nm

Best With…

Product Name	Description	Presentation sheet

SESAME BiV	Standard Cells for direct battery connection	Available

Architectural implementation

A Dual Voltage implementation with the Dolphin Panoply enables to halve the dynamic power consumption at SOC level.

Ask for more information about our Low Power - Dual Voltage Panoply 65 nm, please click here

Standard cells Memories