Panoply 180 / 160 / 152 nm: Low Power - Dual Voltage
To satisfy demanding customers, Fabless companies are facing the need to embed always more features in their chip. The increasing complexity of SoC results in both an increased silicon area and an increased power consumption. To be efficient, power management must be managed at the architectural level.
To facilitate power optimized implementation, Dolphin Integration is introducing a Panoply of Memories, Standard Cells and regulators which uniquely offer Dual Voltage capability and are delivered with characterizations for 1.8 V and 1.1 V in the 180 nm G process node.
⇒ See possible Architectural implementation
| Typical gains |
Core VDD
+/-10% |
Consumption at Nominal Voltage * |
Consumption at Low Voltage * |
| 180 nm G |
1.8 V
1.1 V |
Divided by up to 3.5 |
Divided by up to7 |
* Comparison with traditional libraries
Catalogue
Due to the diversity of foundries, process nodes and variants addressed, make sure to check with us the availability of any Panoply.
⇒ See our complete Catalogue for 180 nm
Best with
| Product Name |
Description |
Presentation sheet |
| SESAME BiV |
Standard Cells for direct battery connection |
Available |
| SRI 1.8 1.0 |
Switching Regulator |
Available |
| LRL-1.8∼3.6/0.9∼1.8 |
Linear Regulator |
Available |
Architectural implementation
The power optimized Dual Voltage Panoply is the demonstration of Dolphin Integration’s technical know-how on Low Power Silicon IPs making it the best ally of medical applications, power sensitive nomad applications and battery-driven industrial applications.
The following schematics propose a low dynamic power architectural implementation:
- The dynamic power consumption is reduced by embedding Dual Voltage memories and libraries of standard cells
- Creation of islets with 3 operating modes depending on the sequence of activity: Active, Low Voltage, Extinction
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