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Catalogue > 90 nm > SESAME Battery Interface Voltage TSMC 90 nm LP

SESAME Battery Interface Voltage TSMC 90 nm LP

 

Stem enabling

Direct Battery supply

with Low Leakage

 

THE WINNING ALTERNATIVE TO IN-HOUSE DEVELOPMENT!

The celebrated BIV (Battery Interface Voltage) with its patented Flip-Flop, is now available at 90 nm in addition to 180 nm and 130 nm, for designing SoCs targeting low-power applications.
SESAME BiV, thanks to its design based on 3.3 V transistors, can be applied for two different and complementary purposes:

  • Direct Battery supply: Using the SESAME BIV for synthesizing small logic blocks directly connected to the battery supply with no need for an intermediate regulator.
  • Low Leakage islet: SESAME BIV is the best alternative for synthesizing an always-on logic block, such as Real Time Clock - while maintaining the leakage to the lowest level compared to implementations based on HVt libraries.

 

Key Benefits

  • Direct battery supply
    • Functional from 1.1 V up to 3.6 V thanks to patented flip flops
    • Simple implementation: islets directly powered by the external battery
    • No need for dedicated regulator
  • Low Leakage features
    • Leakage reduction of 40 to 60 times in typical process
    • Possibility to remove regulators and their leakage
  • Consistent kit for a straightforward design-in
    • Isolation cells
    • Ultra Low Leakage Level Shifters
  • Optimal Design for Yield
    • Design methodology ensuring High-Yield circuits despite Mismatch
    • Specification of OCV margins

 

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