tROMet uHDeLL Phoenix 65 LP - instances
PRELIMINARY
Writing its program into a ROM puts paradoxical demands: enabling high-density while postponing the program layers to the least dense levels. PHOENIX is such a late-programmable but dense ROM thanks to a key bit-cell patent for reaching ultra-high-density and low dynamic power with large capacities beyond 1 Mbit. It stars the brand-new proprietary architecture Phoenix optimized for extremely-low leakage. It embeds smart and optimal pre-charge circuitries consuming a mere 1.2 uA for a 6-Mbit instance in TSMC 65 nm LP!
Positioning & Differentiators
Key Features
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Key “two in one” patent on bitcellsl for ultra-high-density with large capacities beyond 1 Mbit
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Ultra-low leakage even with a generic process:
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Optimized for high DfY i.e. no compromise at the expense of Read Margin and any other design margin
Add-on kit & Peripherals (optional
Powerful encoding algorithm
4 encoding possibilities for one bit-cell which can be changed for every bit-cell and also combined with the scrambling feature to mix address references
Scrambling
A scrambler customized for each user according to specific needs: it may include various protection structures involving addressing schemes for word-lines, bit-lines, bit-cells…
Error Correcting Code
An ECC generator is based on the HAMMING algorithm that enables to detect 2 errors and correct one error per word
Flexibility
| Generator flexibility |
Min |
Max |
Granularity |
| Memory Bit Capacity |
1 M |
8 M |
NA |
| Number of Words |
16 k |
512 k |
8 |
| Number of Bits per Word |
8 |
128 |
1 |
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