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Catalogue > HD-LP Panoply 65 nm > sROMet BCD Haumea generator 65 nm TSMC LP / SMIC LL

sROMet BCD Haumea generator 65 nm TSMC LP / SMIC LL

 

Low fabrication costs

Low Power

Patented

 

To maintain or increase their strength on the market, manufacturers of high density consumer and nomad devices must regularly offer more features to their end customers - while maintaining competitive pricing. Because of this trend, finding the best compromise between low power and cost reduction is a significant challenge for SoC designers.
The metal programmable ROM Haumea meets the most demanding power budgets thanks to its smart low power design and its power reduction features. Haumea also allows cost reduction thanks to its high density architecture and Design for Yield.

 

Positioning & Differentiators

positioning

 

 

 

 

deliverable

Key Benefits

  • Power reduction features
    • Decrease of packaging cost
    • Smaller SoC area
  • Decrease of fabrication costs
    • Programmable through via layer between metal layers 1 and 2
    • SoC routing allowed upwards from Metal 3
    • Patented High Density bit cell
    • 5% to 10% denser than contenders
  • Part of the “High Density - Low Power Panoply”
    • Dual port memory array and memory register Eris
    • Single port memory register Aura
    • Single Port memory array Haumea
    • Density and Speed optimized standard cell libraries
  • Optimal Design for Yield
    • Read margin optimized instance by instance
    • Design methodology ensuring High-Yield circuits despite Mismatch
    • Association with LDO for regulated power supply voltages
    • Optional BIST for industrial fabrication test of instances

patented

Add-ons & Peripherals (optional )

Scrambling
A scrambling feature customized for each user according to specific needs: it may include various protection structures involving addressing systems for word-lines, bit-lines, memory bit-cells…

Error Correcting Code
Our ECC generator is based on the HAMMING algorithm which enables to detect two errors and correct one error per word.

ROM Writer
EDA solution from ROM programming


Flexibility

Generator flexibility
Min
Max
Granularity
Memory Bit Capacity
16 k
512 k
NA
Number of Words
2 k
16 k
512
Number of Bits per Word
8
32
2

 

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