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Catalogue > HD-LP Panoply 65 nm > SpRAM BCD Haumea TSMC 65 nm LP generator

SpRAM BCD Haumea TSMC 65 nm LP generator

 

Low fabrication costs

Low Power

Optimal design for yield

 

To maintain or increase their strength on the market, manufacturers of high density consumer and nomadic devices must regularly offer more features to their end customers - while maintaining competitive pricing. Finding the best compromise between low power and cost reduction is a significant challenge for SoC designers.
The single port memory array Haumea meets the most demanding power budgets thanks to its smart low power design and its power reduction features. Haumea also allows cost reduction thanks to its high density architecture and Design for Yield.

 

Positioning & Differentiators

positioning

 

 

 

 

 

 

 

 

deliverable

Key Benefits

  • Power reduction features
    • Ultra low dynamic power: up to 50% less consuming than alternative solution
    • Data retention mode
    • Stand by mode
    • Flexible power routing: power ring or ring-less
    • Byte write/read capability
  • Decrease of fabrication costs
    • 1P3M with routing allowed upwards from Metal 3
    • or 1P4M with M4 partially available for routing
    • Rotatable memory
    • High density memory
  • Decongestion
    • Innovative power line structure
    • Routability of 100% on M4
  • Part of the “High Density - Low Power Panoply”
    • Dual port memory array and memory register Eris
    • Single port memory register Aura
    • Single via-programmable ROM Cassiopeia
    • Density and Speed optimized standard cell libraries
  • Optimal Design for Yield
    • Read margin optimized instance by instance
    • Design methodology ensuring High-Yield circuits despite Mismatch
    • Association with LDO for regulated power supply voltages
    • Optional BIST for industrial fabrication test of instances

 

Available modes and add-ons

Data Retention mode - included
For ultimate leakage savings: only the memory plane and the circuitry for retention would remain powered. Note that this data-retention mode requires 2 VDD power supply lines and one GND.

Byte mode - included
For more flexibility towards ultimate power savings, the capability of Byte-mode can be implemented in the RAM for Read/Write operations.

BIST - optional
The most efficient testing solution for industrial fabrication test of instances

Extinction mode - optional
The memory is shut down by putting the digital signal EXTINCTION to the logic ‘1’. The extinction of memory through a switch reduces drastically the leakage.


Flexibility

Generator flexibility
Min
Max
Granularity
Memory Bit Capacity
16 k
512 k
NA
Number of Words
2 k
16 k
512
Number of Bits per Word
8
32
2

 

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