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Catalogue >HD-LP Panoply 65 nm > SESAME HD TSMC 65 nm LP

SESAME HD TSMC 65 nm LP

 

High Density

Low Power

THE WINNING ALTERNATIVE TO STANDARD FREE LIBRARIES!

To maintain or increase their market share, designers of high density consumer and portable devices must regularly offer more features to their end users - while maintaining competitive pricing. Finding the best compromise between low power and reduced cost is a significant challenge for SoC designers.
The solution is introduced with a complete Panoply optimized for High Density and Low Dynamic Power.
The Panoply includes Single Port and Dual Port Memory Arrays, metal programmable ROMs, Single Port and Dual Port Memory Registers and Standard Cells.
The SESAME HD architecture of Standard Cells is the ideal alternative to Standard «7/8-Tracks free libraries» for its cost and power reduction capabilities due on the one hand to its RCSL (Reduced Cell Stem Library) structure and on the other hand to its innovative cell design based on small transistors. SESAME HD meets the requirements of applications like embedded microcontrollers, high density consumer and portable devices.
To address the main building blocks of SoC Designs, the SESAME HD stem can also be used in stem fusion by a mix with the SESAME LL stem optimized for leakage and with the SESAME HS stem optimized for speed. Speed may be maximized on critical paths and area or leakage minimized on other circuit paths.

 

Positioning & Differentiators

positionning

Just like ants, the small cells of the HD library allow to build complex and highly efficient superstructures

 

 

 

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Key Benefits of the HD Stem

  • High density
    • Up to 5% smaller area compared to free libraries
    • 6-Track high cells
    • Only Metal 1 used for cell design
  • Power reduction features
    • Less dynamic power consumption than free libraries
  • Part of the “High Density - Low Power Panoply”
    • Single port and Dual Port memory arrays
    • Single port and Dual Port memory registers
    • Single via-programmable ROM
  • Easy implementation
    • Delivered with scripts for an automated optimization at each step of the implementation flow (optional)
  • Optimal Design for Yield
    • Design methodology ensuring High-Yield circuits despite Mismatch
    • Specification of OCV margins

SESAME Principles

  • Better Than Free (BTF)
    • Our motto is to design highly differentiated standard cell libraries to guarantee your best RoI
  • Stem fusion
    • The Ultimate flexibility through mixing by synthesizer and Placer and router to enhance either leakage, speed or density depending on the design
    • Higher performance in two focused library stems than in a single CCSL
  • Optimal DfY
    • Mismatch simulation of the proprietary Spinner Cell system
    • 45 corners validation of the proprietary Spinner Cell system

 

SoC ROUTING allowed upwards from Metal1 Compatible with 1P3M SoC Best performances with 1P5M SoC


 

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