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Catalogue > LP-LV Panoply 180 nm > SESAME uHD-BTF LV (1.1 V) TSMC 180 G

SESAME uHD-BTF LV (1.1 V) TSMC 180 G

 

Low Voltage Library

For Low power

And Cost sensitive applications

THE COST EFFECTIVE STEM FOR POWER MANAGEMENT WITH VOLTAGE ISLETS

Reducing the overall power consumption of a SoC is a critical issue for SoC designers, whether for nomad applications or for battery-driven industrial applications. An efficient way to reduce power consumption is to divide the SoC into voltage islets. However, in mature technological processes, SoC designers seeking to decrease power consumption also face the need for fabrication costs reduction.

Dolphin Integration addresses this dual challenge with the SESAME uHD-BTF Low Voltage standard cell library. As opposed to traditional general purpose libraries characterized at lower voltage, the uHD-BTF LV stem is fully optimized for low power designs. With optimized characterizations at low voltage, the uHD-BTF LV stem can be operated at 1.1 V for the 180 nm G process.

 

Positioning & Differentiators

positionning

Just like a camel, the uHD-BTF LV library relies on low power anatomy and two energy humps

stamp

Key Benefits

  • High density
    • Up to 30% smaller area compared to the best high density alternatives
    • High density Flip Flop: the spinner cell system
    • Only Metal 1 used for cell design
  • Power reduction features
    • Low Voltage capability
    • 6 times less dynamic power consumption at low voltage (1.1 V)
    • 3 times less leaky at low voltage in comparison with free libraries
  • Easy architectural implementation
    • 2 level shifters included
    • Other characterizations for different voltage can be provided as add-on for the uHD-BTF LV stem
    • UPF compliant
    • Delivered with scripts for an automated optimization at each step of the implementation flow (optional)
  • Part of the LP-DV Panoply
    • spRAM, dROMet, associated and optimized Linear Regulators (LRL)

 

SESAME Principles

  • Better Than Free (BTF)
    • Our motto is to design highly differentiated standard cell libraries to guarantee your best RoI
  • Stem composition
    • The Ultimate flexibility through mixing by synthesizer and Placer and router to enhance either speed or density depending on the design
    • Higher performance in two focused library stems than in a single CCSL even when free
  • Optimal DfY
    • Mismatch simulation of the Spinner Cell system
    • 45 corners validation of the Spinner Cell system

 

 

SoC ROUTING allowed upwards from Metal1 Compatible with 1P3M SoC Best performances with 1P5M SoC


 

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