tROMet HSL CASSIOPEIA uHDvLC Instances 180 nm
State-of-the-Art proprietary architecture CASSIOPEIA-HSL for tROMet:
- Micro-wordline scheme for low power consumption
- Patented bit-cell featuring ultra-high-density due to the advanced technology of storing 2bits/ cell
Self-sequenced circuitry for ensuring robustness against process deviations.
Powerful encoding algorithm in tROMet (optional): 4 encoding possibilities for one bit-cell which can be changed for every bit-cell and also combined with the scrambling feature to mix the address references.
Flexible pricing models
Embedded memories are licensed as instances (also called cuts) or as generators and are uniquely packaged to address the diversity of needs, be they for a Fabless supplier targeting a single SoC, a Business Unit of a large corporation targeting several fabrication sources, or an ASIC supplier entrusting front-end design to its end-users.
Key Features
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Ultra-High-Density
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Low-power optimization
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Optimized for high design yield
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Functionality guaranteed from 2.0 V down to 1.45 V!
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Reduced leakage current in stand-by mode
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Reduced injection noise into neighboring analog cells
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No cross-talk between bit-lines
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Independent programming ROM Writer (optional)
Flexibility
| Generator flexibility |
Min |
Max |
Granularity |
| Memory Bit Capacity |
1 M |
8 M |
NA |
| Number of Words |
16 k |
512 k |
8 |
| Number of Bits per Word |
8 |
128 |
1 |
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