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Catalogue > LP-DV Panoply 180 nm > SESAME eLC DV SMIC 180 nm EEPROM

SESAME eLC DV SMIC 180 nm EEPROM

 

Dual Voltage

High Speed

Patented

A DUAL VOLTAGE LIBRARY FOR IMPRESSIVE POWER REDUCTION!

Reducing the overall power consumption of a SoC is a critical issue for SoC designers, especially for battery-powered applications.
SESAME eLC DV is the result of Dolphin’s 20 years' low power expertise. As opposed the usual so-called ”dual voltage” libraries which are only basic libraries characterized at lower voltage, the architecture of SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phenomena linked to low voltage. SESAME eLC DV is characterized for 1.8V +/-10% and 1.1V +/-10%

Thanks to its patented implementation, SESAME eLC DV is the optimal solution for applications such as Wireless Sensors, low power MCUs, RFID or Medical.

Positioning & Differentiators

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Just like a camel, the eLC DV library relies on low power anatomy and two energy humps

stamp

Key Benefits of the eLC DV Stem

  • Ultra Low Power consumption
    • Dual Voltage capability
    • 1,5 times less dynamic power consumption at nominal voltage in comparison with standard 7-Track library
    • 4 times less dynamic power consumption at low voltage (1.1 V)
    • Standard cells optimized for low-power at the schematic level
    • Battery life increases
    • Decrease of heat and life stress of the circuit
  • Leakage is divided by up to 2
  • High speed optimized architecture for critical designs
  • High routability & Less silicon
    • Only Metal 1 is used in layout
    • Compatible with 1P3M SoC implementation
    • Clever I/O pins placement
  • Easy architectural implementation
    • 4 level shifters included
    • Other characterizations for different voltage can be provided as add-on
    • UPF/CPF compliant
  • The Dolphin quality
    • Silicon Proven architecture
    • Safe and Patented low voltage operation
  • Part of the LP-DV Panoply
    • spRAM, dROMet, associated and optimized Linear Regulators (iLR) and Switching Regulators (eSR)
positionning

SoC ROUTING allowed upwards from Metal1 Compatible with 1P3M SoC Best performances with 1P5M SoC


 

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