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Catalogue > LP-DV Panoply 180 nm > SESAME eLC TSMC 180 nm G

SESAME eLC TSMC 180 nm G

 

Low Power

High Speed

Patented

A LIBRARY FOR IMPRESSIVE POWER REDUCTION!

The rising demand for battery-powered and RF applications requires library providers to offer innovative solutions based on new design techniques to lower the overall power consumption of a SoC.
SESAME eLC addresses this need by dramatically reducing power consumption compared with other solutions, while offering the possibility to operate at very high speed.

SESAME eLC is the optimal solution for markets like Medical, Wireless, Mobile Phone, RFID, Smart Card or Portable Multimedia!

 

Positioning & Differentiators

positionning

Just like a crocodile, the eLC library is low energy consuming

stamp

Key Benefits

  • Power consumption is reduced by up to 60%
    • Standard cells optimized for low-power at the schematic level
  • Patented
    • Reduction of power consumption through decreased sensitivity to clock edge and delay variation
  • High speed optimized architecture for critical designs
  • High routability
    • Only Metal 1 is used in layout
    • Clever I/O pins placement

 

 

 

 

 

 

 

SoC ROUTING allowed upwards from Metal1 Compatible with 1P3M SoC Best performances with 1P5M SoC


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