Catalogue > HD-LP Panoply 180 nm > dROMet CASSIOPEIA Generator SMIC 180 nm EEPROM dROMet CASSIOPEIA Generator SMIC 180 nm EEPROM   Low fabrication costs Low Power Patented Embedding one key patent for the ROM bit-cell, the metal programmable dROMet is the solution for high density. Its benefits also include low power thanks to the innovative CASSIOPEIA architecture: Smart and optimal pre-charge circuitries enable no leakage in the memory plane and minimize dynamic power consumption through the optimization of pre-charge level during read operations Self-sequenced circuitry for ensuring robustness against process deviations     Key Benefits Ultra low dynamic power Decrease of packaging cost Smaller SoC area 45% less consuming than conventional metal or via ROM Decrease of fabrication costs Metal 1 and Via metal 1-2 programmable ROM Compatible with 1P4M SoC 20% denser than conventional metal or via ROM Low leakage No leakage in memory plane Minimal leakage in memory periphery 60% less leaky than conventional metal or via ROM Optimal DfY Vias half as numerous in comparison with a traditional metal or via ROM CASSIOPEIA Architecture using bigger transistors for optimized read margin and low sensitivity to mismatch   Optional Add-ons and peripherals Scrambling A scrambling feature customized for each user according to specific needs: it may include various protection structures involving addressing systems for word-lines, bit-lines, memory bit-cells… Error Correcting Code Our ECC generator is based on the HAMMING algorithm which enables to detect two errors and correct one error per word. Flexibility Generator flexibility Min Max Granularity Memory Bit Capacity 1 k 1024 k NA Number of Words 256 128 k 1 Number of Bits per Word 4 128 1   Ask for more information, please click here

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