dROMet LP CASSIOPEIA 180 nm UMC / SMIC / CSM / SIL
Embedding one key patent for the ROM bit-cell, the metal programmable dROMet-LP is the
solution for high-density, compatible with a 1P4M technological process. Its benefits also
include low-power thanks to the innovative architecture CASSIOPEIA[SD]:
- Smart and optimal pre-charge circuitries enabling no leakage in memory plane and
minimization of dynamic power consumption through the optimization of pre-charge level
for read operations
- Self-sequenced circuitry for ensuring robustness against process deviations
Positioning & Differentiators
Key Features
-
High-density achieved with the generic
design rules for the highest DfY
(Design for Yield)
-
Low-power consumption
-
No leakage in sleep mode and reduced
leakage in stand-by (no operation) mode
-
Functionality at nominal voltage 1.8 V +/-
10%
Add-on kit & Peripherals (optional )
Scrambling
A scrambling feature customized for each
customer according to specific needs: it may
include various protection structures
involving addressing systems for word-lines,
bit-lines, memory bit-cells…
Error Correcting Code
Our ECC generator is based on the
HAMMING algorithm that enables to
detect 2 errors and correct one error
per word.
Flexibility
| Generator flexibility |
Min |
Max |
Granularity |
| Memory Bit Capacity |
1 k |
1024 k |
NA |
| Number of Words |
256 |
65536 |
1 |
| Number of Bits per Word |
4 |
128 |
1 |
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