Catalogue > 180 nm > Islet Construction Kit for power optimized logic blocks Islet Construction Kit for power optimized logic blocks Low Voltage islet Dual Voltage islet Extinction islet Retention islet   Reducing both dynamic and static power consumption is a permanent concern for SoC Integrators, in nomad and battery-driven consumer and industrial applications. To facilitate the implementation of power optimized logic blocks, Dolphin Integration offers the Islet Construction Kit (ICK). The ICK enables smooth construction and integration of multi voltages, extinction, and retention islets allowing a drastic reduction of power.   Partitioning power of a complex SoC into islets Architects now frequently design ICs with diverse operating modes to minimize power consumption with the objective to extend battery life or to reduce system cost. It is then up to the SoC Integrators to face the challenge of practically implementing the resulting millions gate islets. more… closed… The Islet Construction Kit is a tool box composed of a full set of low power cells enabling a flexible combination of all power management techniques depending on design goals: control of dynamic power and/or control of leakage power.   Islet Construction Kit cells in details SoC Integrators can leverage on advanced activity power control with the Islet Construction Kit. more… closed… Dynamic power can be reduced by lowering the operation voltage of the islet. The supply voltage level will depend on required performances. When various islets running at different voltages are implemented in a design, level shifters are required. Leakage power can be decimated by shutting down unused islets. Extinction islets are achieved with header power switches, isolation cells, always on buffers and inverters. When data retention is necessary, leakage power of the islets can be reduced in retention mode. Building of retention islets is supported via density optimized retention flip-flops.   Fig 1: Schematic and Layout of Header switch Implementation methods with the ICK The ICK provides means for power control by creation of logic islets. Each islet can have its own supply level, can be powered down at the appropriate time, and can have data retention. The ICK includes coarse grain Header switch cells which “switch” on/off the power rails of multiple cells simultaneously, at the islet level. Various methods can be selected for implementing the logic islets: ring, grid, hybrid. The one described below is the grid style implementation. more… closed… Grid style implementation Both always-on power as well as the gated power are placed in grid. Thus, the switch cells can be placed in rows. Fig 2: Floor plan with grid style Optimal leakage savings Designed with long channel PMOS Optimized Switches for best Ion/Ioff ratio Low area overhead Better control of the number of switches High-Density Retention Flip-Flop architecture Safe integration Better control of IR Drop through a finer definition of power switch size and placement Easy implementation Compatible with standard power-intent description (UPF) Implementable with standard synthesis solution Implementable with standard P&R solution including a multi voltage option Implementation guidelines for selecting the number of switches All ICK cells are offered in multiple drive strengths   ICK performances at 180 nm Graph 1: Leakage reduction by technological processes for 1K Logic Gates, in typical design partition (TT; 25°C) In addition to the drastic leakage reduction enabled by the TSMC 180 nm eLL process flavor, medical, industrial and micro-controllers applications requiring ultra low power consumption with the highest density can leverage on the ICK to improve the RoI of their SoCs. Graph 2: Leakage reduction by modes for 1K Logic Gates at 180 nm eLL, in typical design partition (TT; 25°C)   The ICK represents the first step towards a new generation of SoCs Comprised of islets with several states of activity impacting power consumption Centralized Power Activity management but decentralized Power Switches Openness to embedding the power management units State registers for every islet: necessary and sufficient data for its control by the ACU Ultimate solution for minimizing Power consumption, both dynamic and Static Unique EDA solution for Power Savings assessment (SCROOGE) Dolphin Integration Panoply at 180 nm eLL For building this new generation of complex SoCs, the ICK is part of a complete Panoply of Silicon IPs. This Panoply includes diverse building blocks and enables an optimization of each cells of the design at each step of the design flow: small registers, logic blocks, memories, test network, power management network.       Foundry Sponsored Single Port RAM Memory PLUTON generator for cooling up to 100 times leakage beyond stand-by mode Foundry Sponsored SESAME HD Standard Cell Library for High Density logic blocks, operating at both nominal and low-voltage for further dynamic power saving Patented libraries of standard cells SESAME uHD-BTF for ultra high density logic blocks and SESAME eLC for power sensitive logic islets Patented SESAME BIV (Battery Interface Voltage) library enabling direct battery connection with a leakage divided by up to 1,000 compared to standard library StorageWare: synthesizable models for storage functions, solutions for assembly at soft and hard levels Power Management Solutions Ask for more information, please click here

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