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Catalogue > 130 nm > SESAME uHD-BTF TSMC/SMIC 130 nm G

SESAME uHD-BTF TSMC/SMIC 130 nm G

 

Ultra High Density stem

for Cost reduction

A LIBRARY FOR COST REDUCTION!

SoC designers are under strong pressure to reduce silicon costs.
Standard « free libraries » with average performances are a good solution for very low volumes but as long as high fabrication volumes are concerned, only the highest density guarantees the best RoI.
SESAME uHD-BTF is the solution of choice for cost reduction capability due on the one hand to its RCSL (Reduced Cell Stem Library) structure and on the other hand to its innovative cells design. The uHD-BTF stem is particularly fit for applications like multimedia players, USB controllers, RFID and GPS/PDA.

 

Positioning & Differentiators

positionning

Just like ants, the small cells of the uHD-BTF library allow to build complex and highly efficient superstructures

stamp

Key Benefits

  • High density
    • Up to 10% smaller area compared to the best high density alternatives
    • High density Flip Flop: the spinner cell system
    • 6 Track
    • Only Metal 1 used for cell design
  • Power reduction features
    • 30% less dynamic power consumption at nominal voltage in comparison with free libraries
  • Part of the HD-LP Panoply
    • To optimize the whole SoC for high density and low power
    • Power consumption is decreased by up to 50% and density is increased by up to 10% at SoC level
    • spRAM, dROMet, speed optimized Standard Cell Library, HS-BTF, associated and optimized Linear Regulators (LRL)
  • Easy implementation
    • Delivered with scripts for an automated optimization at each step of the implementation flow (optional)

 

SESAME Principles

  • Better Than Free (BTF)
    • Our motto is to design highly differentiated standard cell libraries to guarantee your best RoI
  • Stem composition
    • The Ultimate flexibility through mixing by synthesizer and Placer and router to enhance either speed or density depending on the design
    • Higher performance in two focused library stems than in a single CCSL even when free
  • Optimal DfY
    • Mismatch simulation of the Spinner Cell system
    • 45 corners validation of the Spinner Cell system

 

SoC ROUTING allowed upwards from Metal1 Compatible with 1P3M SoC Best performances with 1P5M SoC


 

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