Catalogue > 130 nm > tROMet LP Cassiopeia 130 GP tROMet LP Cassiopeia 130 GP PRELIMINARY   Writing into a ROM its program puts paradoxical demands: enabling high-density while postponing the program layers to the least dense levels. CASSIOPEIA is such a late-programmable ROM thanks to a key patent for reaching ultra-high-density for large capacities starting at 1 Mbit with a silicon area lower than 0.5 mm2!!   Positioning & Differentiators   Key Features Key patent “two in one” for ultra high- density for large capacities starting at 1 Mbit Low-leakage even in generic process: no leakage in memory plane Low -power consumption Optimized for high DfY i.e. no compromise at the cost of design margins such as read margin Protection against piracy thanks to : patented bit cell and customized scrambling capabilities.       Add-on kit & Peripherals (optional ) Powerful ROM Writer By programming 2 bits per transistor, 4 decoding possibilities per cell requires a powerful ROM Writer allowing multiple programming. The Scrambling advantage The address scrambling feature customized for each users' needs may include protection structures involving addressing schemes for wordlines, bit-lines, memory bitcells… Error Correcting Code Our ECC generator is based on the HAMMING algorithm which enables at once detecting 2 errors and correcting one error per word. Flexibility Generator flexibility Min Max Granularity Memory Bit Capacity 1 M 8 M NA Number of Words 16 k 512 k 1 Number of Bits per Word 8 128 1   Ask for more information, please click here

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