Catalogue > HD-LP Panoply 130 nm > sROMet LCL Cassiopeia generator TSMC 130 G sROMet LLA Cassiopeia generator TSMC 130 G   Low fabrication costs Low Power Low Leakage   Reducing the overall power consumption of a SoC is a critical issue for SoC designers, especially for portable applications. The already celebrated Cassiopeia architecture for ROM has been designed to address the needs of low power SoCs and is now enriched with an “LLA” release enabling SoC designers to reduce even further the static consumption. The ROM Cassiopeia LLA is thus optimized to attain ultra-low power consumption both dynamic and static along with maintaining good density and speed.   Positioning & Differentiators   Key Benefits Ultra low dynamic power Designed to minimize power consumption up to 50% less power consumption Decrease of fabrication costs Single metal layer via programmable ROM High Density architecture and bit cell 5% to 30% denser than contenders Ultra Low leakage no leakage in memory plane minimal leakage in memory periphery     Add-ons & Peripherals (optional ) Scrambling A scrambling feature may be customized for each user according to specific needs: it may include various protection structures involving addressing systems for word-lines, bit-lines, memory bit-cells… Error Correcting Code Our ECC generator is based on the HAMMING algorithm which enables to detect two errors and correct one error per word. Flexibility Generator flexibility Min Max Granularity Memory Bit Capacity 1 k 1024 k NA Number of Words 256 128 k 8 Number of Bits per Word 4 128 1   Ask for more information, please click here

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