Catalogue > LP-LV Panoply 130 nm > sROMet LLA CASSIOPEIA LV generator TSMC 130 G

sROMet LLA CASSIOPEIA LV generator TSMC 130 G

Low fabrication costs

Low Power

Despite dynamic power reduction made possible by more advanced process nodes, the increasing complexity of designs results in a real challenge to get power consumption back in control.

To address this power challenge, a solution is to select a multiple voltage architecture with blocks running independently at different voltages depending on the operating modes. However, this demands a complete solutions for all elements of the logic design.

The solution is introduced with a complete Low Voltage Panoply of memory arrays, memory registers and standard cells by Dolphin Integration. The Low Voltage Panoply is characterized for 0.9 V for the 130 nm technological process

Positioning & Differentiators

Key Benefits

Power reduction features

Low voltage capability
Designed to minimize power consumption
Up to 75% less power consumption

Decrease of fabrication costs

Single metal layer via programmable ROM
High Density architecture and bit cell
5% to 30% denser than contenders

Ultra low leakage

No leakage in memory plane
Minimal leakage in memory periphery

Part of the “Low Voltage Panoply”

spRAM Haumea LV
HD LV standard cell library
1PRFile Aura LV
Associated and optimized Linear Regulators (LRL)

Optional add-ons & Peripherals

Error Correcting Code
Our ECC generator is based on the HAMMING algorithm which enables to detect two errors and correct one error per word.

Scrambling
A scrambling feature may be customized for each user according to specific needs: it may include various protection structures involving addressing systems for word-lines, bit-lines, memory bit-cells…

Flexibility

Generator flexibility	Min	Max	Granularity
Memory Bit Capacity	1 k	1024 k	NA
Number of Words	256	128 k	8
Number of Bits per Word	4	128	1

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Standard cells Memories