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Catalogue > LP-LV Panoply 130 nm > DpRFile BDS Eris LV generator SMIC / TSMC 130 G

DpRFile BDS Eris LV generator SMIC / TSMC 130 G

PRELIMINARY

High Density

Low Power / Low Voltage

 

Despite dynamic power reduction made possible by more advanced process nodes, the increasing complexity of designs results in a real challenge to get power consumption back in control.

To address this power challenge, a solution is to select a multiple voltage architecture with blocks running independently at different voltages depending on the operating modes and frequency targets. However, this demands a complete solutions for all elements of the logic design.

The solution is introduced with a complete Low Voltage Panoply of memories, registers and standard cells by Dolphin Integration. The Low Voltage Panoply is characterized for 0.9 V +/-10% for the 130 nm technological process and includes:

  • The Density optimized Standard Cell Library, SESAME HD LV.
  • The One Port Register File (1PRFile) Aura LV architecture optimized for high density and speed.
  • The spRAM Haumea LV architecture optimized for low dynamic power and density.
  • The Eris architecture of dual port memory register (2R/2W) which allows power and cost reduction.

 

Positioning & Differentiators

positioning

 

deliverable

Key Benefits

  • Power reduction features
    • Low voltage capability: power consumption is divided by 2 in comparison with traditional solutions
    • Flexible power routing: power ring or ring-less
    • Optional Byte write and bit-wise write capability
  • Flexible architecture
    • Column-mux options can be chosen
    • Wide flexibility for words and bits per word
    • 2R / 2W Ports
  • Decrease of fabrication costs
    • Up to 30% denser than foundry sponsored solutions
    • Optional High Density BIST for industrial fabrication test of instances
  • Decrease of Time-To-Market
    • Layout compatibility with shrink processes
    • Layout compatibility between various foundries
  • Part of the “Low Voltage Panoply”
    • SpRAM Haumea LV and 1PRFile Aura LV
    • HD LV standard cell library
    • Associated and optimized Linear Regulators (LRL)
  • Optimal Design for Yield
    • Design methodology ensuring High-Yield circuits despite Mismatch thanks to the innovative features of our in-house simulator, SMASH

 

Available modes & add-ons

Byte mode and bit-wise - optional
For more flexibility towards ultimate power savings, the capability of Byte-mode can be implemented in the RAM for write operations.

HD BIST - optional
The most efficient testing solution for industrial fabrication test of instances.

Flexibility

Generator flexibility
Min
Max
Granularity
Memory Bit Capacity
128
32 k
NA
Number of Words
4
1 k
2
Number of Bits per Word
8
128
2

 

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