DpRFile BDS Erisgenerator SMIC / TSMC 130 G
To maintain or increase their market share, designers of high density consumer and portable devices must regularly offer more features to their end customers - while maintaining competitive pricing. Finding the best compromise between lower power and reduced cost is a significant challenge for SoC designers.
The solution is introduced with a complete Panoply optimized for High Density and Low Dynamic Power.
The Panoply includes Single Port and Dual Port Memory Arrays, metal programmable ROMs, Single Port and Dual Port Memory Registers and unique standard cells.
The Eris architecture of dual port memory register (2R/2W) allows power and cost reduction while satisfying the speed constraint of many high speed applications for consumers (gaming or DTV for example) and some portable devices like advanced cell phones.
A Low Voltage and a Dual Voltage variants of this product are also available.
Positioning & Differentiators
Key Benefits
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Flexible architecture
- Column-mux options can be chosen
- Wide flexibility for words and bits per word
- 2R / 2W Ports
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Ultra high speed
- Up to 350 Mhz in worst case
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Decrease of fabrication costs
- Up to 30% denser than foundry sponsored solutions
- Optional High Density BIST for industrial fabrication test of instances
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Power reduction features
- Flexible power routing: power ring or ring-less
- Optional Byte write and bit-wise write capability
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Decrease of Time-To-Market
- Layout compatibility with shrink processes
- Layout compatibility between various foundries
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Part of the “High Density - Low Power Panoply”
- Single port and Dual Port memory arrays
- Single via-programmable ROM
- Density and Speed optimized standard cell libraries
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Optimal Design for Yield
- Design methodology ensuring High-Yield circuits despite Mismatch thanks to the innovative features of our in-house simulator, SMASH
Available modes & add-ons
Byte mode and bit-wise - optional
For more flexibility towards ultimate power savings, the capability of Byte-mode can be implemented in the RAM for write operations.
HD BIST - optional
The most efficient testing solution for industrial fabrication test of instances.
Flexibility
| Generator flexibility |
Min |
Max |
Granularity |
| Memory Bit Capacity |
128 |
32 k |
NA |
| Number of Words |
4 |
1 k |
2 |
| Number of Bits per Word |
8 |
128 |
2 |
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