1PRFile BDS Aura LV generator SMIC 130 G
PRELIMINARY
High Speed |
High Density |
in Symphonie LP-LV Panoply |
Despite dynamic power reduction made possible by more advanced process nodes, the increasing complexity of designs results in a real challenge to get power consumption back in control.
To address this power challenge, a solution is to select a multiple voltage architecture with blocks running independently at different voltages depending on the operating modes. However, this demands a complete solutions for all elements of the logic design.
The solution is introduced with a complete Low Voltage Panoply of memory arrays, memory registers and standard cells by Dolphin Integration. The Low Voltage Panoply is characterized for 0.9 V for the 130 nm technological process
Positioning & Differentiators
Key Benefits
Available modes and add-ons
Byte mode - optional
For more flexibility towards ultimate power savings, the capability of Byte-mode can be implemented in the RAM for write operations.
HD BIST - optional
The most efficient testing solution for industrial fabrication test of instances.
Flexibility
| Generator flexibility |
Min |
Max |
Granularity |
| Memory Bit Capacity |
128 |
64 k |
NA |
| Number of Words |
4 |
2 k |
2 |
| Number of Bits per Word |
8 |
128 |
2 |
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