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silicium estimator

Differentiator

 

AHM simulation of the Pop-up Noise

What is the challenge at stake?

AHM

Thanks to the Application Hardware Modeling (AHM), SoC developers can address this topic (noise) which is due to application schematics, application software, ViC-set (set of components surrounding the embedded ViC), thus taking in consideration all the possible sources of noise for ensuring the safest solution at every level.
End-users then can release final devices with top system-level performances.

The main goal is to perform the best compromise between the real performances targeted and the characteristics of the various components in the chain to achieve the lowest cost for the targeted Virtual Component: for instance, avoiding any overestimation of the SNR - as anticipation of further loss of performances after system building - is a way to avoid any over-sizing and / or over-consumption of the ViC.
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Application Hardware Simulation interferes at multi-levels: ViC, SoC, PCB, system

MAIN GOAL
Ensuring targeted performances of the final device to be developed
Performed thanks to Application Hardware Simulation!

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Sample Rate Converter SRC-ADF

schematics

Targeted Application

  • Applications based on streaming
  • Audio Video synchronization

Key Benefits

  • Audio frequency offset adjustment for Audio/Video synchronization or wireless data transmission synchronization
  • Audio quality insurance with better resilience to jitter on audio master clock and serial data interface clock
  • Asynchronous audio data flow adjustment (e.g. for audio real-time streaming like SPDIF)
  • I2S interface of audio converter in slave mode.

Data synchronization may be a strong issue for system makers. It thus requires a wise thinking from Fabless providers for addressing system needs such as: audio / video synchronization, audio data flow adjustment for audio real-time streaming applications, while ensuring high sound quality.

Our audio converters dedicated to applications with such needs embed a Sample Rate Converter. The SRC-ADF (Sample Rate Converter - Asynchronous Discret Frequencies) is specifically dedicated to applications based on real-time streaming. It benefits from a two steps automatic synchronization on Word Clock:

  • A coarse synchronization automatically adapts the input data on one of standardized sample rates (from 8 kHz to 96 kHz), which is very useful for changes in the audio stream, such as zapping or voice to audio changes
  • A fine synchronization then handles small frequency shifts around the chosen sample rate with small steps.

 

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Ensure SoC silicon success on first pass

analog part sensitive

Promote yield-drop free design:

  • Architectures less sensitive to process parameters thanks to patented "Imbalance Locate" simulations
  • Design margins adapted to several foundries models.
  • Performances specified and guaranteed from worst case to best case.

 

Ensure robustness of CODEC architecture against noise from substrate and logic circuitry
=> STRIDE™

 

Guarantee high Power Supply Rejection Ratio
=>Integrated Power-supply controller and DC-DC converters as elements of configuration
integration circuit

Identify and reduce Pop-up-Noise sources at ViC and SoC level,
=> Specific design, smoothing drivers and precise integration rules

 

 

Get rid of a dedicated PLL on SoC and its associated jitter
=> Patented PLL-less option!

 

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