SoC Engineering Support
SoC Integrators face problems of a new kind to ensure an efficient launch into fabrication, in comparison with IC designers, from the insertion of virtual components of which they do not "master" the impact.
Moreover, while such a mission requires Product Engineers as counterparts to cope with the problems encountered in fabrication, there is not even one in a Silicon Foundry.
Key Strengths
Problems addressed
? Defect diagnostic
? Test duration
? Yield analysis
? Reliability issues
DESCRIPTION OF SERVICE
- 1- Verification of compatibility between target feature and performance of SoC and ViC specification
2- A complete understanding of the SoC fab launching process
3- Mastership of ISO-9001 principles and practices (from prototyping to volume fab)
4- A pragmatic sense of relative fabrication costs
5- Training and practice of collective problem-solving
6- Consistency check of the validation plan for silicon test and qualification with the test specification at SoC level
7- Structured tracking of identified symptoms
8- Team-work management for handling failure analysis (root cause analysis)
9- Authority to obtain additional measurements or check-outs
10- Defect modeling and simulation prior to premature conclusion
11- Ultimate choice and management of problem correction
Description of the support
The benefits of our SoC Engineering Support:
SoC Development Support
Dealing with VSIA's Black Box (functional modeling and Testability issues)
Import of Mixed Signal Virtual Components in a pure logic environment
Matching of analog peripherals and embedded software applications
Caring for Noise resilience and Power-consumption
Verification of Jitter and signal integrity at SoC level
Definition of test strategy at chip level, be it a testchip or a SoC for mass production
PRODUCT Engineering
- Specification discrepancies may result in malfunctioning of SoC within application
- Suspicious behavior toward ESD (Electrical Static Discharge ) and EMI (Electro-Magnetic Interference)
- Need for additional power-supply lines and pads for drops, SSO?(Simultaneous Switching Outputs)?
TEST Programming
Test coverage analysis (analysis of BIST, JTAG et al.)
Test programs amenable to adaptative duration
- Critical approval process of validation plan
PROCESS engineering
Design Yield assessment relative to actual fab yield
Comparison with forecast yield possibly different from fab standards (abacus)
Reliability analysis depending on design and process (Electro-migration, aging?)
Industrial TEST Engineering
Calibration of silicon measurements with simulation results
Correlating with Laboratory Functional Test
- Quality control of hardware and software testbenches as too common disturbance sources
- Statistical analysis of defect rates paving the way to yield improvement
PACKAGING Engineering
Wise selection of pads and buffers appropriate for the selected package
Relative Placement of pads depending on specific package
Packaging Yield assessment relative to actual fab yield
Mastery of reliability issue for selected package
