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Specific competencies dedicated to your needs

The customer can rely on Harmonie and its 7 service delivrables to succeed his project with harmony…

 

 

Harmonie offers its 25 years of experience of structuralist and topologist competency. On one hand, from the integratable specification to the reticle, on the other hand, from the FPGA to the SoC, Harmonie covers all needs with a proper know-how to supply its customers.

Seven services

 

 

 

Service for Custom Fabless Product (as part of II and III)

  • Economic and technical feasibility study
  • Integratable specifications
  • Breadboarding and emulation
  • Selection and follow up or IP providers, foundry and test & packaging houses
  • Reduced Bill Of Material
  • Hierarchical SoC Integration Flow
  • Virtual Test and Diagnostic (also for IV)
  • Prototype Characterization

 

Overview of each service deliverable

7 services

I. From Netlist to Layout

  • Final Floorplan with power supply path optimization for IR Drop limitation: placement and power grid sizing rules
  • Power analysis through EDA solutions from Dolphin: SCROOGE Family
  • SCROOGE TLA: Topographical Load Analysis
  • Clock path optimization
  • Routing guidelines for power supply and clock path in order to respect power and noise templates provided in ViC specifications (jitter template for clock, power supply noise template for power supply)

II. RTL to Layout

  • 4 seasons scripts: data path, placement, clock tree, routing => for higher density or for high speed or for low power consumption. An interseason is pending for Energy Islet design
  • Design with Islets, using either Power Extinction and Retention Kit from Dolphin and a cascade of power regulators dedicated to performances of each islet
  • Early Floorplan within SLED provides the block Netlist for Power and Noise analysis:
    • SCROOGE ENA: Early Noise Assessment to validate the placement of blocks (regulator with its sensitive analog block versus logic blocks for example)

III. From Specification to Layout

  • Power Management Network:
    • PMN: full hierarchy or regulators for supplying each islet with the power needed for reaching performances
    • PMNx: to supply an eXternal islet
  • Bug Tracking Network: to secure the preservation of performances during the integration of the ViC into the SoC
  • Power analysis:
    • SCROOGE EPA: Early Power Assessment to validate the regulator choice and to provide constraints in power supply path routing
    • SCROOGE XXL at the architecture level, for a management of the complete power consumption budget for each mode

IV. From ViCs to Super ViC

  • Complete Review of integration risks by introducing and respecting integration guidelines to guarantee the integration of critical functions for the customer
  • One regulator for guaranteeing each ViC performances
  • Partnerships with other SoC Integrators for complementary skills and solutions, for enhanced platforms
  • A Bug Tracking Network of “detectors” including:
    • Built-in Self Characterization
    • Profile to Template matching
  • A Failure Testing Network including
    • Built-in Real-time Debug
    • Built-in Self Test
  • Application Hardware Modeling: for optimizing system level performances (Pop-up Noise, SNR, Jitter etc.)

more information…

V. From FPGA to SoC

  • To reduce the BoM, the power consumption
  • From low volume production to high volume fabrication
  • Multi foundry access

VI. From FPGA to ASC

  • Application Hardware Modeling: for optimizing system level performances (Pop-up Noise, SNR, Jitter etc.)
  • FPGA test on board

VII. From Layout to Reticule

  • Foundry portal with Design Kit access and support
  • Aggregation of several layouts on the same reticule