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Low Power Design

 

Low Power Silicon IPs

Low Power EDA Platform

25 years of expertise

 

Reducing the power consumption is one of the major issues for SoC designers and Silicon IP providers. Analysis power early in the design flow is key to efficient power reduction, and the EDA solutions must enable deep analysis all along the SoC development.
Harmonie, the Dolphin Integration custom fabless service line, offers wide expertise for low design: optimized design, low power Silicon IPs, and dedicated EDA platform. Its extensive expertise in optimization of design makes HARMONIE the perfect match for your SoC development.

 

HARMONIE Added Value

LP Design
  • Harmonie benefits from EDA solutions enabling early power consumption estimation and reduction: the earlier power consumption issues are detected, the lower the development costs
  • 25 years of experience in integration providing to Harmonie a deep knowledge. As a result, Harmonie is able to design a completely low power optimized ASIC for low consumption thanks to specific know-how: power grid rules, functional clock gating, placement & route rules etc.
  • Harmonie benefits from standard EDA solutions and from secret weapons coming from Dolphin Integration:
    • Low power Silicon IPs:
      • RAMs and ROMs
      • Standard cells libraries with power retention switches, level shifters and isolation cells enabling to divide up to 5,000 the leakage @ 65 nm
      • Cache controller optimized to reduced up to 8 times the power consumption of the couple CPU + main memory
    • A complete offering for a Power Management Network (PMN)
      • Voltage controllers for voltage Islet: LDO, DC-DC improved by low noise option for CODECs
      • Detectors for validating templates versus profiles between every unit of the PMN
    • EDA Solutions:
      • SCROOGE EPA for Early Power Assessment and SCROOGE XXL (at the architectural level), for power consumption analysis

 

Why design with Power Islets?

Each application requires specific power supply for each component. The objective is to minimize power consumption through several functional modes thanks to voltage islets. The power islets will impact the power consumption thanks to retention islets or extinction islets. A completely new test strategy is required around a Failure Test Network (FTN) with an Islet architecture.
For more information on the islets design, the SESAME-Power islets Brochure is available on request.

 

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