Position Statement on business Ethics for fabrication

 

Professional practices in any business can be improved by eliminating any temptation of biased decision making, even before any wrongdoing has been committed. Collected warnings reported by prospects during competitive negotiations have inspired the following.

Conflict of interest

Integrated Device Makers charge their deliverables in proportion to the number of units good at the level of packaged ICs (pay-per-part). Meanwhile the foundry business model consists in charging at the level of wafers accepted in accordance with the quality of processing demonstrated by "Reliability and Yield Control Structures" scattered along the scribe lines (pay-per-wafer). This is true even when the deliverables ultimately are tested and packaged only if good for delivery by the foundry. In other words, Foundries deliver wafers, whatever their yield at the level of ICs!

Now Virtual Components (ViC) contribute to IC yield in two opposite ways: namely area density versus area yield, whereas a good design is one that optimizes a trade-off toward the targeted highest yield. Relaxing rules away from design closest to minimum dimensions, may help reduce the frequency of some fabrication defects. In that sense, there are two temptations for foundries towards their choice of a SIP Provider (for Silicon Intellectual Property):

• increasing the ViC complexity for increasing the direct need for wafers in proportion to silicon area (by reducing the number of candidate ICs), is an invisible trick as long as such a ViC is not delivered as a layout, but at RTL (soft) or netlist (firm) levels, promoted with an attractive low cost,
• claiming for higher performances (in speed, power, or noise…) by applying lower quality thresholds of worst-case acceptance, at the cost of lower yield for increasing the indirect need for wafers, with the additional pain of unpredictability of the ultimate number of good ICs.

The former temptation is directly controlled by the obvious appearance of size, so that in fact Foundries place an excessive emphasis on size minimization, at the expense of the latter: the invisible and hardly predictable yield.
For instance, it takes a Platinum simulator to actually help forecast the impact of Offset on yield, thanks to its patented algorithms.

The latter temptation takes even more technical savvy as worst-case modeling depends not only on the simulation conditions, but much more on the all too often implicit benchmark.
For instance, it takes a Platinum simulator to actually help perform an appropriate benchmarking thanks to its capability for Virtual Tests and Diagnostics.

This dual issue appears noticeably in variants called "Pushed Rules" mostly applied to memory bit-cells, and "Relaxed Rules" mostly to enable using a circuit at a voltage higher than the standard maximum. It is aggravated by the choice of more expensive technological variants to the standard processes like the extra MIM layers, of not "General Purpose" options.

Freeware is no free ride

"Free" IP has been promoted by some foundries as a convenient payment scheme whereby the user of some "captive" library cells or Virtual Components would not be charged any NRE for such Technology Access. The true cost of being charged through some pay-per-use scheme is not made clear as long as the hidden impact of such Free IP upon fabrication yield is not known.
Take a PLL not guaranteed to work in all conditions: does it truly mean that non functional operating conditions can be safely identified?
For some enlightenment, see our page on "long-term jitter assessment for your SoC".
While promotion of Freeware is presented as a liberation movement in the Software Engineering industry, it is tantamount to a sting in Silicon Design.

Confusing complexity of the issue

Case in point: reducing the safety margin of worst-cases, over process conditions and operating conditions, may render attractive some design 20 % smaller, while decreasing yield by 30 %.
Alternately, reducing the safety margin of worst-cases over process conditions only, may make acceptable a given design with operating performances 20 % higher, with the same yield reduction of 30 %.
This is a source of confusion for most users, and there is yet another: reducing the safety margin of worst-cases over operating conditions only, may make acceptable a given design with process controls about 30 % worse, i.e. much cheaper to manage, with potentially some drop of reliability over the component lifetime, a dimension rarely accounted for.
The mere difficulty for most engineers, and worse for most purchasing managers, of grasping such subtle issues with drastic economic impact, is the real reason for the Silicon IP Industry to be in such a state of uncertainty about its scheduling of transitions to finer geometries.

Haste not, want not

Professionalism thus invites on the one hand, Prospects to ensure the total independence of SIP Providers with respect to Foundries… and on the other hand, SIP Providers to make public their worst-case acceptance criteria.
Prospects should be put in a position where they could make an educated guess at least, a conscious choice at best.
DOLPHIN has waged campaigns about basic criteria for reliable SoC Integration, beginning with:

• threshold for acceptance of Embedded Memories with respect to Read-margins
  For a more complete assessment, see "an enlightening Yield IQ"
  
• criteria for acceptance of Phase-Lock Loops with respect to Long Term Jitters
  

The case for pushed rules

When a common ViC design presents some highly repetitive cell, it is conceivable to minimize this cell layout, but some trial-and-error search technique that may leave performances and yield invariant. In other words a new topological design rule must be identified with satisfactory electrical parameters.
Of course, this technique common for embedded memory planes is a highly professional and economically attractive solution for a foundry to increase the direct number of candidate ICs per wafer.
The opportunity is left to compatible IDM's to find appropriate pushed rules for competitive embedded memories with higher performance/complexity potential.

DOLPHIN specialists may provide guidance as to which rules should be pushed prior to silicon qualification for the ViC so that users may get the best of both worlds, design and fabrication.

The case for pure logic versus yield

The classical "compromise with truth" is to claim that a single implementation of some logic virtual Component can at the same time be the densest and fastest! Not only has DOLPHIN moved away from such pretense, but they encourage a second order improvement:

• a processor like Flip 8051 Storm has been split from its twin Flip 8051 Cyclone, whereby the former had been optimized for minimum complexity, versus the latter optimized for maximum speed, and the same is true for its 80251 successors
• a strong recommendation is documented for the user to be consistent throughout the VSIA levels, thus to synthesize accordingly: for the densest netlist through the choice of cell library as offered by SESAME, then synthesizer parametrization, then Placement and Routing
  

Royalty payment for a three-way win-win deal

There can be no good deal, neither for many a buyer wanting a free ride, nor for the supplier wanting as irresponsibly to make no commitment so as to face no risk. The only way for the ViC user to get a commitment to success from SIP Providers is to ensure that it be a joint success!
While SoC Integration implies that several ViC components must play properly with each other, yield and reliability still are considered as individual contributions from each SIP provider. Occasionally, buyers will give preference to some EDA Editor bundling tools and a portfolio of diverse ViC. But what does count, is reaching a collective commitment to high yield: a commitment of all contributors financially interested through Royalty payments sufficiently attractive!
Case in point: with separate providers for some processor and a PLL, or a processor and an embedded memory, should not they both be concerned with the proper interworkings so that they may cash-in?

Implicit judgements versus explicit benchmarking

It is traditional that programmers provide "default values" which are totally meaningless: e.g. default parameters in SPICE, without relationship with a specific process. It hurts a misoriented novice user, so that the DOLPHIN practice is to provide a minimal tutorial together with an explicit "Figure of Merit": e.g. FoM for RagTime embedded memories.
Even the traditional benchmarks for computer performance tend to be absurdly parametrized: Whetstones and Dhrystones with default parameters misguide the user who should not be deceived at a time when he engages in a complex SoC Integration problem. For enhancing trust, each DOLPHIN Product Line strives both to deliver simple benchmarks and to document them explicitly: e.g. Flip 8051 performance comparisons.

Competition with customers

We hereby invite our visitors to contribute their points of view on other potential conflicts of interest, and we intend to focus particularly on the two following areas. The result shall be guidelines to communicate on this web-site.

Any need to separate the charters?

• Chipless Providers of ViC versus Fabless Suppliers of standard ICs?
• Editors of CAD tools versus service providers for integrating them into some CAD Framework?
• Design Centers as custom SIP Providers versus Chipless Providers of standard ViC?
  

Feel free to send your concerns to integration@dolphin-integration.com.