Year 2010 |
| July 23 |
Availability of the HD-LP Panoply at 130 nm for reducing SoC area up to 20%
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| July 9 |
A cutting-edge solution for the smooth integration of a precise measurement Converter into a SoC
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| July 2 |
Upgrade of SLED and SMASH delivering block-busting innovation
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| June 25 |
A new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10%
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| June 14 |
An ultra High Density Library decreasing the 130 nm logic area up to 30%
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| May 28 |
Tired from facing data synchronization with loss of performance?
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| May 17 |
Dolphin Integration complements their portfolio of ROM with a shrinked variant of Cassiopeia for the 152 nm process
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| May 10 |
Dolphin Integration concentrates on cost-cutting with the Standard Cell Library HD-BTF for 65 nm processes
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| May 3 |
Promotion of equivalence checking for multi-level modeling
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| April 26 |
How to save development time for your application program?
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| April 19 |
Customization for market needs comes to a turning point
with our Codec Configurator
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| March 26 |
Availability of a brand new Front End generator: spRAM Haumea for the 130 nm G process
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| March 22 |
Dolphin Integration completes their catalog of Standard Cell Libraries with a new stem optimized for low leakage: LL-BTF
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| March 1 |
EMBLEM-MATH: a library of mathematical equations to build complex behavioral models
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| February 22 |
Widening of our catalog with libraries targeting both Low Power and High Speed
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| January 29 |
Availability of a complete FREE evaluation kit for a Memory CACHE controller
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| January 25 |
The embedded audio CODEC with smallest power consumption on the market!
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| January 18 |
Strengthening of our portfolio of Standard Cell libraries with the DUAL innovation targeting Low Power designs
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