Pulsed latch based library to get the best area
Discover how our ultra high-density standard cell library (SESAME uHD) can be used smoothly in standard design flows…
How to safely design a low-power SoC
With Maestro™, developing and verifying the ACU/PMU-logic of a low-power SoC becomes a hassle-free task, managing both the modes of power domains and the states of regulators and oscillators. Discover the best-in-class solution for the control of power islands...
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Design Automation Conference
June 06-08, 2016
Austin, United States